Description: The objective of this projectis to design, model and simulate an autocorrelation
generator circuit using 4-bit LFSR. the register and LFSR will used D flip-flop and some
gates. By the autocorrelation concept, there should be 2 same length vectors, for calculating
the autocorrelation , we have to design the register for storing the original vector and the
shifter for make time delay.
-The objective of this projectis to design, model and simulate an autocorrelation generat or circuit using 4-bit LFSR. the register and LF SR will used D flip-flop and some gates. By the au tocorrelation concept, there should be two same length vectors, for calculating the autocorrelation. we have to design the register or for storing the iginal vector and the shifter for make time Abuelas y. Platform: |
Size: 13259 |
Author:yangzq |
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Description: The objective of this projectis to design, model and simulate an autocorrelation
generator circuit using 4-bit LFSR. the register and LFSR will used D flip-flop and some
gates. By the autocorrelation concept, there should be 2 same length vectors, for calculating
the autocorrelation , we have to design the register for storing the original vector and the
shifter for make time delay.
-The objective of this projectis to design, model and simulate an autocorrelation generat or circuit using 4-bit LFSR. the register and LF SR will used D flip-flop and some gates. By the au tocorrelation concept, there should be two same length vectors, for calculating the autocorrelation. we have to design the register or for storing the iginal vector and the shifter for make time Abuelas y. Platform: |
Size: 13312 |
Author:yangzq |
Hits:
Description: 在Quartus下使用D触发器来加入延迟，每个D触发器增加半个周期的延迟，稍加更改可以得到不同的延迟。-In Quartus using D flip-flop to join the delay, each D flip-flop raised a half-cycle delay, a little change can be a different delay. Platform: |
Size: 377856 |
Author:桃子 |
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Description: 一、实验目的
掌握I/O地址译码电路的工作原理。
二、实验原理和内容
译码输出端Y0～Y7在实验台上“I/O地址当CPU执行I/O指令且地址在280H～2BFH范围内，译码器选中，必有一根译码线输出负脉冲。利用这个负脉冲控制L7闪烁发光（亮、灭、亮、灭、……），时间间隔通过软件延时实现。
三、编程提示
1、实验电路中D触发器CLK端输入脉冲时，上升沿使Q端输出高电平L7发光，CD端加低电平L7灭。-1, experiment aims to master I/O address decoding circuitry works. 2, experimental principle and content of the decoder outputs Y0 ~ Y7 in the experimental stage, " I/O address when the CPU implementation of the I/O instruction and the address is 280H ~ 2BFH within the decoder is selected, there must be a decoding line output negative pulse. take advantage of this negative impulse control L7 flashing LED (light, eliminate, brighter, silencers, ... ...), time interval delay achieved through software. 3, programming tips an experimental circuit D flip-flop CLK-ended input pulse when the rising edge so that Q-ended output high L7 LED, CD-side plus low L7 destroy. Platform: |
Size: 13312 |
Author:杨洁 |
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Description: 0.最简单的SystemC程序：hello, world.
1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。
2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。
3.如何在SystemC中实现延时（类似verilog中的#time）的例子。
4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实也演示了在sc_signal中如何使用用户自定义的struct。
5.构造函数带参数的例子。
6.轮转仲裁的例子。
7.使用类摸板的例子。
8.如何在模块中包含子模块。
9.SystemC的Transaction级验证示例。
10.如何trace一个数组
11.SystemC中使用测试向量文件输入的例子。
12.SystemC采用UDP/TCP通信的例子。
13.Cadence的ncsc的例子。
-0 most simple SystemC program: hello, world.
A D flip-flop using SystemC example also demonstrates how to generate VCD waveform files.
Synchronous FIFO example using SystemC. FIFO is from the same folder fifo.v (Verilog code) translated.
Delay (similar to verilog# time). In SystemC examples.
4.SystemC document the "User Guide" in the example. Note the slightly different cultural block is modified the packet.h file, reload = << operator. In fact, this also demonstrates how to use user-defined struct in sc_signal.
Constructor with parameters example.
(6) examples of web arbitration.
7. The class Moban examples.
8 module contains a sub-module.
9.SystemC of Transaction-Level Verification example.
10 How to trace an array
11.SystemC use the example of the test vector file input.
12.SystemC using the example of the UDP/TCP communication.
Examples of 13.Cadence the ncsc. Platform: |
Size: 532480 |
Author:sdd |
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Search - D Flip flop delay